1. Field of the Invention
This invention relates to semiconductor integrated circuits and, more particularly, to integrated circuits utilizing voltage generation.
2. State of the Art
Semiconductor devices such as metal-oxide semiconductor (MOS) devices or transistors are comprised of four terminals: gate, source, drain, and bulk. The connection integrity of these terminals is critical for proper operation and device longevity. For example, in p-channel MOS (PMOS) devices, the source terminal is generally connected to the highest voltage potential of any other terminal of the device, meaning the source is generally more positive in voltage than, for example, the drain terminal. Similarly important is that the bulk terminal of the transistor must be at a potential equivalent to the most positive of either the source or drain terminals in order to mitigate the possibility of the transistor locking up into an inoperable and even destructive state, known by those of skill in the art as the “latch-up” condition.
In a simplified design, the bulk terminal is generally connected directly to the source terminal since the source terminal is generally more positive in voltage potential than the drain terminal. However, there are situations, such as in charge pump applications, where the source terminal of the transistor can assume a lower voltage potential than the drain terminal of the transistor. In such a scenario, a latch-up condition can occur if the bulk terminal is connected to the source terminal of the transistor since the drain terminal would have a higher voltage potential than the bulk terminal. It should be reiterated that the latch-up condition is not just an impairment to the circuit, but rather a latch-up condition can result in destruction of an entire circuit and associated system. Therefore, it would be an advantage to provide a mechanism that minimizes such occurrences.